tb Architecture Reference

Architecture tb of drv8711_spi_tb entity. More...

Functions
string	to_string ( vector: in std_logic_vector )
	Function to create string from std_logic_vector.

Processes
pr_clock	( )
	Clock generator process.
pr_stimulus	( )
	Stimulus process to drive PWM unit under test.

Constants
c_clk_period	time := 10 ns
	Test bench clock period.
c_stimulus	t_stimulus_array := ( ( name = > " Transfer " , data_wr = > X " A501 " , data_rd = > X " 0000 " ) , ( name = > " Transfer " , data_wr = > X " AAAA " , data_rd = > X " 0000 " ) , ( name = > " Transfer " , data_wr = > X " 5555 " , data_rd = > X " 0000 " ) )
	Test stimulus.

Types
t_stimulus_array	array ( natural range <> ) of t_stimulus
	Stimulus array type.

Signals
clk	std_logic
	Clock input to uut.
rst	std_logic
	Reset input to uut.
data_send	std_logic_vector ( 15 DOWNTO 0 )
	Data to send.
data_recv	std_logic_vector ( 15 DOWNTO 0 )
	Data received.
xfer_adv	std_logic
	Transfer advance pulse.
xfer_start	std_logic
	Transfer start flag.
xfer_done	std_logic
	Transfer done pulse.
spi_scs	std_logic
	SPI chip-select line.
spi_sclk	std_logic
	SPI clock line.
spi_mosi	std_logic
	SPI mosi line.
spi_miso	std_logic
	SPI miso line.
xfer_clk_rst	std_logic
	Reset transfer clock.

Records
t_stimulus
	Stimulus record type.
name	string ( 1 TO 30 )
	Stimulus name.
data_wr	std_logic_vector ( 15 DOWNTO 0 )
	Write data to gpio_device.
data_rd	std_logic_vector ( 15 DOWNTO 0 )
	Expected read data from gpio_device.

Instantiations
i_uut	drv8711_spi <Entity drv8711_spi>
	Instantiate DRV8711 SPI as uut.
i_xfer_clk	clk_div_n <Entity clk_div_n>
	Instantiate clk_div_n for transfer clock.

Detailed Description

Architecture tb of drv8711_spi_tb entity.

Definition at line 17 of file drv8711_spi_tb.vhd.

Member Function Documentation

pr_clock()

pr_clock

(

)

Clock generator process.

This generates the clk signal and the adv signal

Definition at line 120 of file drv8711_spi_tb.vhd.

    pr_clock : PROCESS IS
    BEGIN
    
        clk <= '0';
        WAIT FOR c_clk_period / 2;

        clk <= '1';
        WAIT FOR c_clk_period / 2;
        
    END PROCESS pr_clock;

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The documentation for this class was generated from the following file:

• fpga/common/devices/sim/drv8711_spi_tb.vhd