tb Architecture Reference

Architecture tb of step_generator_tb entity. More...

Processes
pr_clock	( )
	Clock generation process.
pr_stimulus	( )
	Stimulus process to drive PWM unit under test.

Use Clauses
rst
	rst input to uut
count
	count input to uut
delay
	delay input to uut

Constants
c_clk_period	time := 10 ns
	Test bench clock period.
c_stimulus	t_stimulus_array := ( ( name = > " Hold in reset " , rst = > ' 1 ' , count = > B " 000 " , delay = > B " 000 " , rise = > 0 , fall = > 0 ) , ( name = > " No steps " , rst = > ' 0 ' , count = > B " 000 " , delay = > B " 000 " , rise = > 0 , fall = > 0 ) , ( name = > " One step " , rst = > ' 0 ' , count = > B " 001 " , delay = > B " 111 " , rise = > 1 , fall = > 1 ) , ( name = > " Two steps " , rst = > ' 0 ' , count = > B " 010 " , delay = > B " 100 " , rise = > 2 , fall = > 2 ) , ( name = > " Three steps " , rst = > ' 0 ' , count = > B " 011 " , delay = > B " 011 " , rise = > 3 , fall = > 3 ) , ( name = > " Four steps " , rst = > ' 0 ' , count = > B " 100 " , delay = > B " 010 " , rise = > 4 , fall = > 4 ) , ( name = > " Five steps " , rst = > ' 0 ' , count = > B " 101 " , delay = > B " 001 " , rise = > 5 , fall = > 5 ) , ( name = > " Six steps " , rst = > ' 0 ' , count = > B " 110 " , delay = > B " 001 " , rise = > 6 , fall = > 6 ) , ( name = > " Seven steps " , rst = > ' 0 ' , count = > B " 111 " , delay = > B " 000 " , rise = > 7 , fall = > 7 ) , ( name = > " Overrun " , rst = > ' 0 ' , count = > B " 111 " , delay = > B " 111 " , rise = > 3 , fall = > 2 ) )
	Test stimulus.

Types
t_stimulus_array	array ( natural range <> ) of t_stimulus
	Stimulus array type.

Signals
clk	std_logic
	Clock.
enable	std_logic
	Enable input to uut.
advance	std_logic
	Advance input to uut.
step	std_logic
	Step output from uut.
edge_rst	std_logic
	Reset edge counter.
edge_rise	integer
	Count of rising edges.
edge_fall	integer
	Count of falling edges.

Records
t_stimulus
	Stimulus record type.
name	string ( 1 TO 20 )
	Stimulus name.
rise	integer
	Expected rise count.
fall	integer
	Expected fall count.

Instantiations
i_uut	step_generator <Entity step_generator>
	Instantiate step_generator as unit under test.
i_adv_divisor	clk_div_n <Entity clk_div_n>
	Instantiate clk_div_n to generate advance pulses every 4th clock.
i_edge_count	sim_edge_count <Entity sim_edge_count>
	Instantiate edge counter to analyze edges.

Detailed Description

Architecture tb of step_generator_tb entity.

Definition at line 20 of file step_generator_tb.vhd.

Member Data Documentation

count

count

Package

count input to uut

Count input to uut.

Definition at line 26 of file step_generator_tb.vhd.

delay

delay

Package

delay input to uut

Delay input to uut.

Definition at line 27 of file step_generator_tb.vhd.

rst

rst

Package

rst input to uut

Reset.

Definition at line 25 of file step_generator_tb.vhd.

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The documentation for this class was generated from the following file:

• fpga/common/utility/sim/step_generator_tb.vhd