rtl Architecture Reference

Architecture rtl of top entity. More...

Processes
pr_reset	( clk , lock )
	Reset process.
pr_spi_input	( clk , rst )
	SPI input double-flop resynchronizer.

Components
osch
	Component declaration for the MachX02 internal oscillator.
pll
	Component delcaration for the PLL.

Signals
osc	std_logic
	Internal oscillator (11.08MHz)
lock	std_logic
	PLL Lock.
clk	std_logic
	Main clock (99.72MHz)
rst_ms	std_logic
	Reset (possibly metastable)
rst	std_logic
	Reset.
spi_cs_ms	std_logic
	SPI chip-select input (metastable)
spi_sclk_ms	std_logic
	SPI clock input (metastable)
spi_mosi_ms	std_logic
	SPI MOSI input (metastable)
spi_ver_en_ms	std_logic
	SPI Version Enable (metastable)
spi_cs_s	std_logic
	SPI chip-select input (stable)
spi_sclk_s	std_logic
	SPI clock input (stable)
spi_mosi_s	std_logic
	SPI MOSI input (stable)
spi_ver_en_s	std_logic
	SPI Version Enable input (stable)
pwm_adv	std_logic
	PWM advance signal.
spi_miso_out_device	std_logic
	SPI MISO output for devices.
spi_miso_out_version	std_logic
	SPI MISO output for version.
dat_rd_reg	std_logic_vector ( 95 DOWNTO 0 )
	SPI read data (response)
dat_wr_reg	std_logic_vector ( 95 DOWNTO 0 )
	SPI write data (command)
dat_wr_done	std_logic
	SPI write done pulse.
pwm_lines	std_logic_vector ( 3 DOWNTO 0 )
	PWM outputs.
sdm_lines	std_logic_vector ( 3 DOWNTO 0 )
	SDM outputs.
gpio_in_lines	std_logic_vector ( 31 DOWNTO 0 )
	GPIO inputs.
gpio_out_lines	std_logic_vector ( 31 DOWNTO 0 )
	GPIO outputs.

Instantiations
i_osch	osch
	Instantiate the internal oscillator for 11.08MHz.
i_pll	pll
	Instantiate the PLL (11.08MHz -> 99.72MHz)
i_pwm_clk	clk_div_n <Entity clk_div_n>
	Instantiate the clock divider for PWM advance.
i_spi_slave_device	spi_slave <Entity spi_slave>
	Instantiate SPI slave device bus.
i_spi_slave_version	spi_slave <Entity spi_slave>
	Instantiate SPI slave version bus.
i_pwm_device	pwm_device <Entity pwm_device>
	Instantiate the PWM device.
i_sdm_device	sdm_device <Entity sdm_device>
	Instantiate the PWM device.
i_gpio_device	gpio_device <Entity gpio_device>
	Instantiate the GPIO device.

Detailed Description

Architecture rtl of top entity.

Definition at line 35 of file top.vhd.

Member Function Documentation

pr_reset()

pr_reset	(		clk,
			lock
	)

Reset process.

This process provides a synchronous reset signal where possible. Before the PLL has locked, it asserts reset; and after the PLL has locked it uses the resynchronized reset input pin.

Definition at line 201 of file top.vhd.

    pr_reset : PROCESS (clk, lock) IS
    BEGIN

        IF (lock = '0') THEN
            rst_ms <= '1';
            rst    <= '1';
        ELSIF (rising_edge(clk)) THEN
            rst_ms <= rst_in;
            rst    <= rst_ms;
        END IF;

    END PROCESS pr_reset;

pr_spi_input()

pr_spi_input (   clk ,   rst   )

Process

SPI input double-flop resynchronizer.

This process double-flops the SPI inputs to resolve metastability and ensure the signals are stable for SPI processing

Definition at line 218 of file top.vhd.

    BEGIN

        IF (rst = '1') THEN
            spi_cs_ms     <= '0';
            spi_sclk_ms   <= '0';
            spi_mosi_ms   <= '0';
            spi_ver_en_ms <= '0';
            spi_cs_s      <= '0';
            spi_sclk_s    <= '0';
            spi_mosi_s    <= '0';
            spi_ver_en_s  <= '0';
        ELSIF (rising_edge(clk)) THEN
            spi_cs_ms     <= spi_cs_in;
            spi_sclk_ms   <= spi_sclk_in;
            spi_mosi_ms   <= spi_mosi_in;
            spi_ver_en_ms <= spi_ver_en_in;
            spi_cs_s      <= spi_cs_ms;
            spi_sclk_s    <= spi_sclk_ms;
            spi_mosi_s    <= spi_mosi_ms;
            spi_ver_en_s  <= spi_ver_en_ms;
        END IF;

    END PROCESS pr_spi_input;

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The documentation for this class was generated from the following file:

• fpga/targets/MachX02-7000HE-Breakout/impl1/source/top.vhd