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Verilog Parser
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Verilog Parser
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Fully describes the instantiation of one or more gate level primitives. More...
#include <verilog_ast.h>
Data Fields | |
| union { | |
| struct { | |
| ast_list * pull_gates | |
| ast_primitive_pull_strength * pull_strength | |
| } | |
| ast_enable_gate_instances * enable | |
| ast_n_input_gate_instances * n_in | |
| ast_n_output_gate_instances * n_out | |
| ast_pass_enable_switches * pass_en | |
| ast_switches * switches | |
| }; | |
| ast_metadata | meta |
| Node metadata. | |
| ast_gate_type | type |
Fully describes the instantiation of one or more gate level primitives.
1.8.11 
