Verilog Parser

Describes a single port for a user defined primitive. More...

#include <verilog_ast.h>

Data Fields

union {
   ast_identifier   identifier
 
   ast_list *   identifiers
 IFF direction != input.
 
}; 
 
ast_node_attributes * attributes
 
ast_expression * default_value
 
ast_port_direction direction
 
ast_metadata meta
 Node metadata.
 
ast_boolean reg
 Is a register or wire?
 

Detailed Description

Describes a single port for a user defined primitive.


The documentation for this struct was generated from the following file: