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Verilog Parser
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describes a sequential entry in a udp body. More...
#include <verilog_ast.h>
Data Fields | |
| union { | |
| ast_list * edges | |
| iff entry_prefix == PREFIX_EDGES | |
| ast_list * levels | |
| iff entry_prefix == PREFIX_LEVELS | |
| }; | |
| ast_level_symbol | current_state |
| ast_udp_seqential_entry_prefix | entry_prefix |
| ast_metadata | meta |
| Node metadata. | |
| ast_udp_next_state | output |
describes a sequential entry in a udp body.