|
|
#define | DIR_READ(a) ((a) | (1 << 7)) |
| |
|
#define | DIR_WRITE(a) ((a) & 0x7f) |
| |
|
#define | swap16(w) __builtin_bswap16((w)) |
| |
|
#define | FXAS21002C_DEVICE_PATH_GYRO "/dev/fxas21002c_gyro" |
| |
|
#define | FXAS21002C_DEVICE_PATH_GYRO_EXT "/dev/fxas21002c_gyro_ext" |
| |
|
#define | FXAS21002C_STATUS 0x00 |
| |
|
#define | FXAS21002C_OUT_X_MSB 0x01 |
| |
|
#define | FXAS21002C_OUT_X_LSB 0x02 |
| |
|
#define | FXAS21002C_OUT_Y_MSB 0x03 |
| |
|
#define | FXAS21002C_OUT_Y_LSB 0x04 |
| |
|
#define | FXAS21002C_OUT_Z_MSB 0x05 |
| |
|
#define | FXAS21002C_OUT_Z_LSB 0x06 |
| |
|
#define | FXAS21002C_DR_STATUS 0x07 |
| |
|
#define | DR_STATUS_ZYXOW (1 << 7) |
| |
|
#define | DR_STATUS_ZOW (1 << 6) |
| |
|
#define | DR_STATUS_YOW (1 << 5) |
| |
|
#define | DR_STATUS_XOW (1 << 4) |
| |
|
#define | DR_STATUS_ZYXDR (1 << 3) |
| |
|
#define | DR_STATUS_ZDR (1 << 2) |
| |
|
#define | DR_STATUS_YDR (1 << 1) |
| |
|
#define | DR_STATUS_XDR (1 << 0) |
| |
|
#define | FXAS21002C_F_STATUS 0x08 |
| |
|
#define | F_STATUS_F_OVF (1 << 7) |
| |
|
#define | F_STATUS_F_WMKF (1 << 6) |
| |
|
#define | F_STATUS_F_CNT_SHIFTS 0 |
| |
|
#define | F_STATUS_F_CNT_MASK (0x3f << F_STATUS_F_CNT_SHIFTS) |
| |
|
#define | FXAS21002C_F_SETUP 0x09 |
| |
|
#define | F_SETUP_F_MODE_SHIFTS 6 |
| |
|
#define | F_SETUP_F_MODE_MASK (0x3 << F_SETUP_F_MODE_SHIFTS) |
| |
|
#define | F_SETUP_F_WMRK_SHIFTS 0 |
| |
|
#define | F_SETUP_F_WMRK_MASK (0x3f << F_SETUP_F_WMRK_SHIFTS) |
| |
|
#define | FXAS21002C_F_EVENT 0x0a |
| |
|
#define | F_EVENT_F_EVENT (1 << 5) |
| |
|
#define | F_EVENT_FE_TIME_SHIFTS 0 |
| |
|
#define | F_EVENT_FE_TIME_MASK (0x1f << F_EVENT_FE_TIME_SHIFTS) |
| |
|
#define | FXAS21002C_INT_SRC_FLAG 0x0b |
| |
|
#define | INT_SRC_FLAG_BOOTEND (1 << 3) |
| |
|
#define | INT_SRC_FLAG_SRC_FIFO (1 << 2) |
| |
|
#define | INT_SRC_FLAG_SRC_RT (1 << 1) |
| |
|
#define | INT_SRC_FLAG_SRC_DRDY (1 << 0) |
| |
|
#define | FXAS21002C_WHO_AM_I 0x0c |
| |
|
#define | WHO_AM_I 0xd7 |
| |
|
#define | FXAS21002C_CTRL_REG0 0x0d |
| |
|
#define | CTRL_REG0_BW_SHIFTS 6 |
| |
|
#define | CTRL_REG0_BW_MASK (0x3 << CTRL_REG0_BW_SHIFTS) |
| |
|
#define | CTRL_REG0_BW(n) (((n) & 0x3) << CTRL_REG0_BW_SHIFTS) |
| |
|
#define | CTRL_REG0_BW_HIGH CTRL_REG0_BW(0) |
| |
|
#define | CTRL_REG0_BW_MED CTRL_REG0_BW(1) |
| |
|
#define | CTRL_REG0_BW_LOW CTRL_REG0_BW(2) |
| |
|
#define | CTRL_REG0_SPIW (1 << 6) |
| |
|
#define | CTRL_REG0_SEL_SHIFTS 3 |
| |
|
#define | CTRL_REG0_SEL_MASK (0x2 << CTRL_REG0_SEL_SHIFTS) |
| |
|
#define | CTRL_REG0_HPF_EN (1 << 2) |
| |
|
#define | CTRL_REG0_FS_SHIFTS 0 |
| |
|
#define | CTRL_REG0_FS_MASK (0x3 << CTRL_REG0_FS_SHIFTS) |
| |
|
#define | CTRL_REG0_FS_2000_DPS (0 << CTRL_REG0_FS_SHIFTS) |
| |
|
#define | CTRL_REG0_FS_1000_DPS (1 << CTRL_REG0_FS_SHIFTS) |
| |
|
#define | CTRL_REG0_FS_500_DPS (2 << CTRL_REG0_FS_SHIFTS) |
| |
|
#define | CTRL_REG0_FS_250_DPS (3 << CTRL_REG0_FS_SHIFTS) |
| |
|
#define | FXAS21002C_RT_CFG 0x0e |
| |
|
#define | RT_CFG_ELE (1 << 3) |
| |
|
#define | RT_CFG_ZTEFE (1 << 2) |
| |
|
#define | RT_CFG_YTEFE (1 << 1) |
| |
|
#define | RT_CFG_XTEFE (1 << 0) |
| |
|
#define | FXAS21002C_RT_SRC 0x0f |
| |
|
#define | RT_SRC_EA (1 << 6) |
| |
|
#define | RT_SRC_ZRT (1 << 5) |
| |
|
#define | RT_SRC_Z_RT_POL (1 << 4) |
| |
|
#define | RT_SRC_YRT (1 << 3) |
| |
|
#define | RT_SRC_Y_RT_POL (1 << 2) |
| |
|
#define | RT_SRC_XRT (1 << 1) |
| |
|
#define | RT_SRC_X_RT_POL (1 << 0) |
| |
|
#define | FXAS21002C_RT_THS 0x10 |
| |
|
#define | RT_THS_DBCNTM (1 << 7) |
| |
|
#define | RT_THS_THS_SHIFTS 0 |
| |
|
#define | RT_THS_THS_MASK (0x7f << RT_THS_THS_SHIFTS) |
| |
|
#define | FXAS21002C_RT_COUNT 0x11 |
| |
|
#define | FXAS21002C_TEMP 0x12 |
| |
|
#define | FXAS21002C_CTRL_REG1 0x13 |
| |
|
#define | CTRL_REG1_RST (1 << 6) |
| |
|
#define | CTRL_REG1_ST (1 << 5) |
| |
|
#define | CTRL_REG1_DR_SHIFTS 2 |
| |
|
#define | CTRL_REG1_DR_MASK (0x07 << CTRL_REG1_DR_SHIFTS) |
| |
|
#define | CTRL_REG1_DR_12_5 (7 << CTRL_REG1_DR_SHIFTS) |
| |
|
#define | CTRL_REG1_DR_12_5_1 (6 << CTRL_REG1_DR_SHIFTS) |
| |
|
#define | CTRL_REG1_DR_25HZ (5 << CTRL_REG1_DR_SHIFTS) |
| |
|
#define | CTRL_REG1_DR_50HZ (4 << CTRL_REG1_DR_SHIFTS) |
| |
|
#define | CTRL_REG1_DR_100HZ (3 << CTRL_REG1_DR_SHIFTS) |
| |
|
#define | CTRL_REG1_DR_200HZ (2 << CTRL_REG1_DR_SHIFTS) |
| |
|
#define | CTRL_REG1_DR_400HZ (1 << CTRL_REG1_DR_SHIFTS) |
| |
|
#define | CTRL_REG1_DR_800HZ (0 << CTRL_REG1_DR_SHIFTS) |
| |
|
#define | CTRL_REG1_ACTIVE (1 << 1) |
| |
|
#define | CTRL_REG1_READY (1 << 0) |
| |
|
#define | FXAS21002C_CTRL_REG2 0x14 |
| |
|
#define | CTRL_REG2_INT_CFG_FIFO (1 << 7) |
| |
|
#define | CTRL_REG2_INT_EN_FIFO (1 << 6) |
| |
|
#define | CTRL_REG2_INT_CFG_RT (1 << 5) |
| |
|
#define | CTRL_REG2_INT_EN_RT (1 << 4) |
| |
|
#define | CTRL_REG2_INT_CFG_DRDY (1 << 3) |
| |
|
#define | CTRL_REG2_INT_EN_DRDY (1 << 2) |
| |
|
#define | CTRL_REG2_IPOL (1 << 1) |
| |
|
#define | CTRL_REG2_PP_OD (1 << 0) |
| |
|
#define | FXAS21002C_CTRL_REG3 0x15 |
| |
|
#define | CTRL_REG3_WRAPTOONE (1 << 3) |
| |
|
#define | CTRL_REG3_EXTCTRLEN (1 << 2) |
| |
|
#define | CTRL_REG3_FS_DOUBLE (1 << 0) |
| |
|
#define | DEF_REG(r) {r, #r} |
| |
|
#define | FXAS21002C_MAX_RATE 800 |
| |
|
#define | FXAS21002C_DEFAULT_RATE FXAS21002C_MAX_RATE |
| |
|
#define | FXAS21002C_MAX_OUTPUT_RATE 280 |
| |
|
#define | FXAS21002C_DEFAULT_RANGE_DPS 2000 |
| |
|
#define | FXAS21002C_DEFAULT_FILTER_FREQ 30 |
| |
|
#define | FXAS21002C_TEMP_OFFSET_CELSIUS 40 |
| |
|
#define | FXAS21002C_DEFAULT_ONCHIP_FILTER_FREQ 64 |
| |
|
#define | FXAS21002C_MAX_OFFSET 0.45f |
| | max offset: 25 degrees/s
|
| |
|
#define | FXAS21002C_TIMER_REDUCTION 250 |
| |
|
#define | FXAS21002C_NUM_CHECKED_REGISTERS 6 |
| |
Driver for the NXP FXAS21002C 3-Axis Digital Angular Rate Gyroscope connected via SPI.