Verilog Parser
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caters for procedural_continuous_assignments in Annex A.6.2 of spec. More...
#include <verilog_ast.h>
Data Fields | |
union { | |
ast_single_assignment * assignment | |
The assignment being made. | |
ast_lvalue * lval | |
lvalue being assigned / deassigned. | |
}; | |
ast_metadata | meta |
Node metadata. | |
ast_hybrid_assignment_type | type |
Type of hybrid assignment. | |
caters for procedural_continuous_assignments in Annex A.6.2 of spec.
this is needed because the spec describes something it calls procedural continuous assignments. I think these are procedural in the programatic / statement sense, but are continous in the time domain during a simulation.