Verilog Parser

Fully describes a single loop statement. More...

#include <verilog_ast.h>

Data Fields

union {
   ast_list *   generate_items
 IFF type == LOOP_GENERATE;.
 
   ast_statement *   inner_statement
 Loop body.
 
}; 
 
ast_expression * condition
 Condition on which the loop runs.
 
ast_single_assignment * initial
 Initial condition for for loops.
 
ast_metadata meta
 Node metadata.
 
ast_single_assignment * modify
 Modification assignment for for loop.
 
ast_loop_type type
 The type of loop.
 

Detailed Description

Fully describes a single loop statement.


The documentation for this struct was generated from the following file: