Module Port Declaration

Data Structures
struct	ast_port_declaration
	Fully describes a single port declaration. More...

Enumerations
enum	ast_net_type {   NET_TYPE_SUPPLY0, NET_TYPE_SUPPLY1, NET_TYPE_TRI, NET_TYPE_TRIAND,   NET_TYPE_TRIOR, NET_TYPE_TRIREG, NET_TYPE_WIRE, NET_TYPE_WAND,   NET_TYPE_WOR, NET_TYPE_NONE }
	Describes the type of a net in Verilog. More...

Functions
ast_port_declaration *	ast_new_port_declaration (ast_port_direction direction, ast_net_type net_type, ast_boolean net_signed, ast_boolean is_reg, ast_boolean is_variable, ast_range *range, ast_list *port_names)
	Creates and returns a new port declaration representation. More...

Detailed Description

Enumeration Type Documentation

enum ast_net_type

Describes the type of a net in Verilog.

Enumerator
NET_TYPE_SUPPLY0	Logic 0 supply rail.
NET_TYPE_SUPPLY1	Logic 1 supply rail.
NET_TYPE_TRI	Tri-state.
NET_TYPE_TRIAND	Tri-state AND.
NET_TYPE_TRIOR	Tri-state OR.
NET_TYPE_TRIREG	Tri-state reg wire.
NET_TYPE_WIRE	Wire.
NET_TYPE_WAND	?
NET_TYPE_WOR	?
NET_TYPE_NONE	Use only when not specified!

Function Documentation

ast_port_declaration* ast_new_port_declaration	(	ast_port_direction	direction,
		ast_net_type	net_type,
		ast_boolean	net_signed,
		ast_boolean	is_reg,
		ast_boolean	is_variable,
		ast_range *	range,
		ast_list *	port_names
	)

Creates and returns a new port declaration representation.

Parameters

[in]	direction	Input / output / inout etc.
[in]	net_type	Wire/reg etc
[in]	net_signed	Signed value?
[in]	is_reg	Is explicitly a "reg"
[in]	is_variable	Variable or net?
[in]	range	Bus width.
[in]	port_names	The names of the ports.