ast_port_declaration Struct Reference

Fully describes a single port declaration. More...

#include <verilog_ast.h>

Data Fields
ast_port_direction	direction
	Input / output / inout etc.
ast_boolean	is_reg
	Is explicitly a "reg".
ast_boolean	is_variable
	Variable or net?
ast_metadata	meta
	Node metadata.
ast_boolean	net_signed
	Signed value?
ast_net_type	net_type
	Wire/reg etc.
ast_list *	port_names
	The names of the ports.
ast_range *	range
	Bus width.

Detailed Description

Fully describes a single port declaration.

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The documentation for this struct was generated from the following file:

• src/verilog_ast.h