Verilog Parser

Decribes a single port connection in a module instance. More...

#include <verilog_ast.h>

Data Fields

ast_expression * expression
 
ast_metadata meta
 Node metadata.
 
ast_identifier port_name
 

Detailed Description

Decribes a single port connection in a module instance.

Note
This is also used to represent parameter assignments.

The documentation for this struct was generated from the following file: