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Verilog Parser
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Describes the instantiation of a module, as opposed to it's declaration. More...
Data Structures | |
| struct | ast_module_instance |
| A single instance of a defined module. More... | |
| struct | ast_module_instantiation |
| Describes the instantiation of one or more modules of the same type with the same parameters. More... | |
| struct | ast_port_connection |
| Decribes a single port connection in a module instance. More... | |
Functions | |
| ast_module_instance * | ast_new_module_instance (ast_identifier instance_identifier, ast_list *port_connections) |
| Creates and returns a new instance of a module with a given identifer and set of port connections. | |
| ast_module_instantiation * | ast_new_module_instantiation (ast_identifier module_identifer, ast_list *module_parameters, ast_list *module_instances) |
| Creates and returns a new set of module instances with shared parameters. | |
| ast_port_connection * | ast_new_named_port_connection (ast_identifier port_name, ast_expression *expression) |
| Creates and returns a new port connection representation. More... | |
Describes the instantiation of a module, as opposed to it's declaration.
| ast_port_connection* ast_new_named_port_connection | ( | ast_identifier | port_name, |
| ast_expression * | expression | ||
| ) |
Creates and returns a new port connection representation.
| port_name | - The port being assigned to. |
| expression | - The thing inside the module the port connects to. |
| port_name | - The port being assigned to. |
| expression | - The thing inside the module the port connects to. |