Verilog Parser

Describes a single statement, and can contain sequential statement blocks. More...

#include <verilog_ast.h>

Data Fields

union {
   ast_assignment *   assignment
 
   ast_statement_block *   block
 
   ast_case_statement *   case_statement
 
   ast_conditional_statement *   conditional
 
   void *   data
 
   ast_disable_statement *   disable
 
   ast_event_expression *   event
 
   ast_function_call *   function_call
 
   ast_generate_block *   generate_block
 
   ast_loop_statement *   loop
 
   ast_module_item *   module_item
 
   ast_task_enable_statement *   task_enable
 
   ast_timing_control_statement *   timing_control
 
   ast_wait_statement *   wait
 
}; 
 
ast_node_attributes * attributes
 
ast_boolean is_function_statement
 
ast_boolean is_generate_statement
 
ast_metadata meta
 Node metadata.
 
ast_statement_type type
 

Detailed Description

Describes a single statement, and can contain sequential statement blocks.

Warning
The data member of the union should never be accessed except when first instantiating the structure. It is used to set the data content and nothing more. This is very bad practice and knowing this code is here pains me dearly.

The documentation for this struct was generated from the following file: