Verilog Parser
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Describes a single statement, and can contain sequential statement blocks. More...
#include <verilog_ast.h>
Data Fields | |
union { | |
ast_assignment * assignment | |
ast_statement_block * block | |
ast_case_statement * case_statement | |
ast_conditional_statement * conditional | |
void * data | |
ast_disable_statement * disable | |
ast_event_expression * event | |
ast_function_call * function_call | |
ast_generate_block * generate_block | |
ast_loop_statement * loop | |
ast_module_item * module_item | |
ast_task_enable_statement * task_enable | |
ast_timing_control_statement * timing_control | |
ast_wait_statement * wait | |
}; | |
ast_node_attributes * | attributes |
ast_boolean | is_function_statement |
ast_boolean | is_generate_statement |
ast_metadata | meta |
Node metadata. | |
ast_statement_type | type |
Describes a single statement, and can contain sequential statement blocks.